A pervasive trend in modern integrated circuit manufacture is to increase the number of data bits stored per unit area on an integrated circuit memory unit, such as a flash electrically erasable programmable read only memory (EEPROM) unit. Memory units often include a relatively large number of core memory devices (sometimes referred to as memory cells), For instance, a conventional charge trapping dielectric flash memory device is capable of storing two bits of data in “double-bit” format. That is, one bit can be stored using a memory cell on a first side of the memory device and a second bit can be stored using a memory cell on a second side of the memory device.
Each memory device is operatively arranged to be programmed, read and erased by the application of appropriate voltage potentials. Typically, the gate electrode of each device can be coupled to a wordline and the source and the drain can each be coupled to a bitline for applying the various voltage potentials to the corresponding components of the memory device.
Programming of such a device can be accomplished, for example, by hot electron injection. Hot electron injection involves applying appropriate voltage potentials to each of the gate electrode, the source, and the drain of the memory device for a specified duration until the charge storing layer accumulates charge. Such a process, with respect to a NOR architecture memory device is disclosed in co-owned U.S. Pat. No. 6,215,702, which is incorporated herein by reference in its entirety.
Erasing of such a device can be accomplished, for example, by hot hole injection. Hot hole injection involves applying appropriate voltage potentials to the gate electrode and the drain, while floating or grounding the source, to erase one of the memory cells (typically the normal bit). Conversely, the complementary bit is erased by floating the drain and applying appropriate voltage potentials to the source and the gate. Alternatively, both the normal and complementary bits can be erased simultaneously.
In a flash memory array, numerous memory cells are typically erased simultaneously. Erasing of the memory cells can be accomplished by repeated applications of short erase pulses, as described above. After each erase pulse, an erase verification can be performed to determine if each cell in the array is “undererased,” (i.e., whether the cell has a threshold voltage above a predetermined limit). If an undererased cell is detected, an additional erase pulse can be applied to the entire array. With such an erase procedure, cells that are not undererased will also be repeatedly erased, leading to some cells becoming “overerased” before other cells are sufficiently erased. A memory cell having a threshold voltage erased below a predetermined limit is commonly referred to as being overerased. In this case, the charge storing layer of the over-erased cells is depleted of electrons and becomes positively charged.
An over-erased condition is undesirable for many reasons. For instance, the programming characteristics of an overerased cell deteriorate more rapidly, affecting, among other things, the number of times that a cell can be reprogrammed. Overerased cells are also undesirable because they can cause bitline leakage current during program and/or read procedures.
In view of the foregoing, a need exists for a device and method of erasing an array of multi-bit memory cells, which reduces overerasing and tightens threshold voltage distribution.